Hard disk drives are commonly used in personal computers (PC's), servers, video recorders, and many other kind of electronic devices for mass storage. Mass storage is used to store large amounts of data that is typically copied to a faster random-access memory such as a dynamic-random-access memory (DRAM) for use by a processor. While the processor's DRAM is randomly accessible, mass storage is block-accessible. An entire block of data must be read or written from the mass storage device. A RAM may allow reading and writing of individual bytes or words of 4 or 8 bytes, while a mass storage device requires that a sector or 512 bytes or more be read or written together.
Flash memory may also be used as a mass storage device in lieu of a hard disk. Flash-memory arrays are also block-accessible, but have a much faster access time than rotating media such as a hard disk. However, since flash memory chips are block-addressable rather than randomly-accessible, flash is not as easy to use for a cache as DRAM or SRAM.
A host generates a logical sector addresses (LSA) of a 512-byte block of data to be read or written from a mass storage device. Flash memory can only be erased a block at a time. A flash memory manager converts LSA logical addresses from a host PC into physical block addresses (PBA) that identify physical blocks of data in the flash memory. The flash memory manager may use re-mapping tables to perform the address translation, and may perform other flash-related functions such as wear-leveling to spread erasures over blocks in flash memory. An erase count may be kept for each block in flash memory, and the block with the lowest erase count is selected to receive new data.
While an entire block has to be erased together, pages within a block could be written and over-written several times. Some older flash memory chips may allow over-writing of pages that have previously been written. Blocks with all stale pages could be erased and re-used.
FIG. 1A is a graph of cell states in an older single-level-cell (SLC) flash memory. Older flash memory chips used electrically-erasable programmable read-only memory (EEPROM) memory cells that stored one bit of data per memory cell. Each cell could be in one of two states. When the floating gate in the flash memory cell was charged with electrons, a higher (more positive) gate voltage is needed to turn on the conducting transistor channel. When the floating gate in the flash memory cell was not charged with electrons, a lower (less positive) gate voltage is needed to turn on the conducting transistor channel.
In FIG. 1A, a gate voltage between VL0 and VL1 is sufficient to cause the transistor to turn on and conduct when the cell was programmed into the low state. When the cell was programmed into the high state, no significant conduction occurs at these lower voltages. Instead, conduction occurs when the gate voltage rises to a voltage between VL1 and VU1 when the cell was programmed into the high state. A single reference voltage VR1 separates the two states of the cell.
The cell state strength (a statistical distribution of cells) is a maximum between lower and upper voltages VL0, VU0 for the low or 0 state when properly programmed. The cell state strength for the high or 1 state is a maximum between voltages VL1, VU1. When the cell is programmed correctly, sufficient noise margin is provided and the cell states do not overlap.
FIG. 1B shows cell states in a newer multi-level-cell (MLC) flash memory. Newer flash memory chips use EEPROM memory cells that stored two, four, or more bits of data per memory cell. Different amounts of charge stored on the floating gates produce different current and different sensing voltages for the same memory cell. Thus a single memory cell can store multiple bits of information by assigning different voltages to different logic levels.
For example, sensing voltages above VR3, near Vcc, are read as a logic 11, while sensing voltages below VR1 near ground are interpreted as a logic 00. Voltages above VR2 and below VR3 are a logic 10, and voltages below VR1 but above VR1 are a logic 01. The normal logic states can have a narrower voltage range, such as VL0, VR0.
Cells are carefully programmed with just the right amount of charge to produce voltages within one of the four ranges. During programming, the allowable voltage ranges are further reduced to add a noise margin. As cells are programmed, they can be read for their sensing voltage, and programming stopped when the sensing voltage is near the middle of the desired range.
For example, when writing the cell into state 01, the cell is programmed so that the sensing voltage is between the narrower range of VL1, VU1. During reading, any voltage in the wider range of VR1 to VR2 is read as state 01. Thus the difference between VL1 and VR1, and also between VR2 and VU1, are noise margins.
FIG. 1C shows cell states in a 16-level MLC flash memory. Each flash cell stores 4 binary bits of data, and has 16 levels or states. State 1111 is programmed to create a sensing voltage between VL0, VU0, and is sensed during reading when the sensing voltage is below VL1. State 1110 is programmed to create a sensing voltage between VL1, VU1, and is read as any voltage between VR1, VR2. State 0001 is programmed to create a sensing voltage between VL14, VU14, and is read as any voltage between VR14, VR15. State 0000 is programmed to between VL15, VU15, and read as voltages above VR15. There are a total of 16 states for each flash-memory cell.
Multi-level-cell flash memory can store a higher density than single-level cell flash for the same cell size. Thus multi-level cell flash is likely to be used more frequently for higher-density flash chips made now and in the future. However, MLC flash chips may impose additional restrictions on usage. For example, a MLC flash chip may not allow pages to be written a second time before erase. Instead, the entire block must be erased before any page can be written again. Each page may be written only once after each erase. Alternately, some writing may be allowed, such as writing a 1 bit to a 0 bit, but other writes are not allowed, such as writing a 0 bit to a 1 bit. Some MLC flash chips may be even more restrictive, only allowing pages to be written in a sequence within a block, and not allowing pages to be written out-of-order.
Another problem with MLC cells, especially with many states per cell, is that the noise margins are very small. Over time, floating gates can gain or lose charge. Programming or reading adjacent cells may disturb stored charge, or leakage may occur. Cells that were programmed to the middle of their range, such as VL14 to VU14 for state 14, may eventually drift outside of their programmed range (VL14, VU14). Once cells drift outside of their reading range (VR14, VR15 for state 14), then the wrong cell state is read, and a data failure occurs.
While MLC cells with a high number of states per cell is desirable for improved density, data failures from read or program disturbs, or leakage, becomes a greater problem as the number of states per cell increases and the noise margins decrease. A flexible management scheme that compensates for the smaller noise margins is desirable. Using error correction such as Reed-Solomon Error Correction Code (ECC) can repair small data errors, but when even a single multi-level cell fails, a string of multiple bits may fail that is not correctable using ECC.
What is desired is a flash memory manager for MLC flash memory. A flash memory manager that downgrades the number of bits per cell is desirable.